? semiconductor components industries, llc, 2008 september, 2008 ? rev. 0 1 publication order number: NB7V586M/d NB7V586M 1.8v differential 2:1 mux input to 1.2v/1.8v 1:6 cml clock/data fanout buffer / translator multi ? level inputs w/ internal termination description the NB7V586M is a differential 1 ? to ? 6 cml clock/data distribution chip featuring a 2:1 clock/data input multiplexer with an input select pin. the inx/inx inputs incorporate internal 50 termination resistors and will accept differential lvpecl, cml, or lvds logic levels (see figure 12). the inx/inx inputs and core logic are powered with a 1.8 v supply. the NB7V586M produces six identical differential cml output copies of clock or data. the outputs are configured as three banks of two differential pair. each bank (or all three banks) have the flexibility of being powered by any combination of either a 1.8 v or 1.2 v supply. the 16 ma differential cml output structure provides matching internal 50 source terminations and 400 mv output swings when externally terminated with a 50 resistor to v cco x (see figure 11). the 1:6 fanout design was optimized for low output skew and minimal jitter and is ideal for sonet, gige, fiber channel, backplane and other clock/data distribution applications operating up to 6 ghz or 10 gb/s typical. the v refac reference outputs can be used to rebias capacitor ? coupled differential or single ? ended input signals. the NB7V586M is offered in a low profile 5x5 mm 32 ? pin pb ? free qfn package. application notes, models, and support documentation are available at www.onsemi.com. the NB7V586M is a member of the gigacomm ? family of high performance clock products. features ? maximum input data rate > 10 gb/s typical ? data dependent jitter < 10 ps ? maximum input clock frequency > 6 ghz typical ? random clock jitter < 0.8 ps rms, max ? low skew 1:6 cml outputs, 20 ps max ? 2:1 multi ? level mux inputs ? 175 ps typical propagation delay ? 50 ps typical rise and fall times ? differential cml outputs, 330 mv peak ? to ? peak, typical ? operating range: v cc = 1.71 v to 1.89 v ? operating range: v cco x = 1.14 v to 1.89 v ? internal 50 input termination resistors ? v refac reference output ? qfn32 package, 5 mm x 5 mm ? ? 40 c to +85 c ambient operating temperature ? these are pb ? free devices marking diagram* qfn32 mn suffix case 488am http://onsemi.com *for additional marking information, refer to application note and8002/d. see detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. ordering information simplified logic diagram 32 1 nb7v 586m awlyyww 1 a = assembly location wl = wafer lot yy = year ww = work week g or = pb ? free package q0 q0 q1 q1 q2 q2 q3 q3 q4 q4 q5 q5 v cco1 v cco2 v cco3 v cc sel v refac0 in0 vt0 in0 in1 vt1 in1 v refac1 v cc gnd 0 1
NB7V586M http://onsemi.com 2 gnd 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 16 in1 in1 in0 gnd vcc02 q3 q3 q2 q2 gnd vcc02 vrefac0 in0 vt1 vrefac1 vt0 figure 1. 32 ? lead qfn pinout (top view) NB7V586M exposed pad (ep) nc vcc03 q5 q5 q4 q4 vcc03 gnd sel vcc q0 q0 q1 q1 vcc01 table 1. input select function table sel* clk input selected 0 in0 1 in1 *defaults high when left open. table 2. pin description pin name i/o description 1,4 5,8 in0, in0 in1, in1 lvpecl, cml, lvds input non ? inverted, inverted, differential inputs 2,6 vt0, vt1 internal 100 center ? tapped termination pin for in0/in0 and in1/in1 31 sel lvttl/lvcmos input input select pin; low for in0 inputs, high for in1 inputs; defaults high when left open 10 nc ? no connect 30 vcc ? 1.8 v positive supply voltage for the inputs and core logic. 25 vcco1 1.2 v or 1.8 v positive supply voltage for the q0, q0 , q1, q1 cml outputs 18, 23 vcco2 ? 1.2 v or 1.8 v positive supply voltage for the q2, q2 , q3, q3 cml outputs 11, 16 vcco3 1.2 v or 1.8 v positive supply voltage for the q4, q4 , q5, q5 cml outputs 29, 28 27, 26 q0, q0 q1, q1 1.2 v or 1.8 v cml output non ? inverted, inverted differential outputs; powered by vcco1 (notes 1 and 2). 22, 21 20, 19 q2, q2 q3, q3 1.2 v or 1.8 v cml output non ? inverted, inverted differential outputs; powered by vcco2 (notes 1 and 2). 15, 14 13, 12 q4, q4 q5, q5 1.2 v or 1.8 v cml output non ? inverted, inverted differential outputs; powered by vcco3 (notes 1 and 2). 9, 17, 24, 32 gnd negative supply voltage, connected to ground 3 7 vrefac0 vrefac1 ? output voltage reference for capacitor ? coupled inputs, only ? ep ? the exposed pad (ep) on the qfn ? 32 package bottom is thermally connected to the die for improved heat transfer out of package. the exposed pad must be attached to a heat ? sinking conduit. the pad is electrically connected to the die, and must be electric- ally and thermally connected to gnd on the pc board. 1. in the differential configuration when the input termination pins (vt0, vt1) are connected to a common termination voltage or left open, and if no signal is applied on inn/inn input, then, the device will be susceptible to self ? oscillation. qn/qn outputs have internal 50 source termination resistors. 2. all v cc , vcc0x and gnd pins must be externally connected to a power supply for proper operation.
NB7V586M http://onsemi.com 3 table 3. attributes characteristics value esd protection human body model machine model > 2 kv > 200 v input pullup resistor (r pu ) 75 k moisture sensitivity (note 3) level 1 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in transistor count 308 meets or exceeds jedec spec eia/jesd78 ic latchup test 3. for additional information, see application note and8003/d. table 4. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc positive power supply gnd = 0 v 3.0 v v ccox positive power supply gnd = 0 v 3.0 v v io input/output voltage gnd = 0 v ? 0.5 v io v cc + 0.5 ? 0.5 to v cc + 0.5 v v inpp differential input voltage |in x ? in x | 1.89 v i in input current through r t (50 ? resistor) 40 ma i out output current continuous surge 34 40 ma i vfrefac v refac sink/source current 1.5 ma t a operating temperature range ? 40 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) (note 4) 0 lfpm 500 lfpm qfn ? 32 qfn ? 32 31 27 c/w c/w jc thermal resistance (junction ? to ? case) (note 4) standard board qfn ? 32 12 c/w t sol wave solder pb ? free 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 4. jedec standard multilayer board ? 2s2p (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
NB7V586M http://onsemi.com 4 table 5. dc characteristics ? cml output v cc = 1.8 v 5%, v cco1 = 1.2 v 5% or 1.8 v 5%, v cco2 = 1.2 v 5% or 1.8 v 5%, v cco3 = 1.2 v 5% or 1.8 v 5%, gnd = 0 v, t a = ? 40 c to 85 c (note 5) symbol characteristic min typ max unit power supply current (inputs and outputs open) i cc i cco power supply current for v cc (inputs and outputs open) power supply current for vccox (inputs and outputs open) 75 95 125 105 ma cml outputs (note 6) v oh output high voltage v cc = 1.8 v, vccox = 1.8 v v cc = 1.8 v, vccox = 1.2 v v ccox ? 40 1760 1160 v ccox ? 20 1780 1180 v ccox 1800 1200 mv v ol output low voltage v cc = 1.8 v, vccox = 1.8 v v cc = 1.8 v, vccox = 1.2 v v ccox ? 500 1300 700 v ccox ? 400 1400 800 v ccox ? 275 1525 925 mv differential inputs driven single ? ended (note 7) (figure 6) v th input threshold reference voltage range (note 8) 1050 v cc ? 100 mv v ih single ? ended input high voltage v th + 100 v cc mv v il single ? ended input low voltage gnd v th ? 100 mv v ise single ? ended input voltage (v ih ? v il ) 200 1200 mv v refac v refac output reference voltage @ 100 a for capacitor ? coupled inputs, only v cc ? 550 v cc ? 450 v cc ? 300 mv differential inputs driven differentially (note 9) (figures 4 and 7) v ihd differential input high voltage (in, in ) 1100 v cc mv v ild differential input low voltage (in, in ) gnd v cc ? 100 mv v id differential input voltage (in, in ) (v ihd ? v ild ) 100 1200 mv v cmr input common mode range (differential configuration, note 10) (figure 9) 1050 v cc ? 50 mv i ih input high current in/in (vto / vt1 open) ? 150 150 a i il input low current in/in (vto / vt1 open) ? 150 150 a control input (sel pin) v ih input high voltage for control pin v cc x 0.65 v cc mv v il input low voltage for control pin gnd v cc x 0.35 mv i ih input high current ? 150 20 +150 a i il input low current ? 150 5 +150 a termination resistors r tin internal input termination resistor (measured from inx to vtx) 45 50 55 r tout internal output termination resistor 45 50 55 note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. input parameters vary 1:1 with v cc . and output parameters vary 1:1 with v ccox . 6. cml outputs (qn/qn ) have internal 50 source termination resistors and must be externally terminated with 50 to v ccox for proper operation. 7. v th , v ih, v il and v ise parameters must be complied with simultaneously. 8. v th is applied to the complementary input when operating in single ? ended mode. 9. v ihd , v ild , v id and v cmr parameters must be complied with simultaneously. 10. v cmr min varies 1:1 with gnd, v cmr max varies 1:1 with v cc . the v cmr range is referenced to the most positive side of the differential input signal.
NB7V586M http://onsemi.com 5 table 6. ac characteristics v cc = 1.8 v 5%, v cco1 = 1.2 v 5% or 1.8 v 5%, v cco2 = 1.2 v 5% or 1.8 v 5%, v cco3 = 1.2 v 5% or 1.8 v 5%, gnd = 0 v, t a = ? 40 c to 85 c (note 11) symbol characteristic min typ max unit f max maximum input clock frequency, v outpp 200 mv 4.0 6.0 ghz f datamax maximum operating input data rate (prbs23) 10 gbps v outpp output voltage amplitude (see figures 4, note 15) f in 4.0 ghz 200 330 mv t plh , t phl propagation delay to output differential @ 1 ghz, in x /in x to q n /q n measured at differential crosspoint sel to q n 125 125 175 250 300 ps t plh tc propagation delay temperature coefficient 100 fs/ c t skew output ? output skew (within device) (note 12) device ? device skew (t pd max ? t pdmin ) 30 50 ps t dc output clock duty cycle (reference duty cycle = 50%) f in 4.0 ghz 45 50 55 % t jitter output random jitter (rj) (note 13) f in 4.0 ghz deterministic jitter (dj) (note 14) 10 gbps 0.2 0.8 10 ps rms ps pk ? pk v inpp input voltage swing (differential configuration) (note 15) 100 1200 mv t r , t f output rise/fall times @ 1 ghz (20% ? 80%) q n , q n 50 65 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. measured using a 400 mv source, 50% duty cycle clock source. all outputs must be loaded with external 50 to v ccox . input edge rates 40 ps (20% ? 80%). 12. skew is measured between outputs under identical transitions and conditions. duty cycle skew is defined only for dif ferential operation when the delays are measured from cross ? point of the inputs to the crosspoint of the outputs. 13. additive rms jitter with 50% duty cycle clock signal. 14. additive peak ? to ? peak data dependent jitter with input nrz data at prbs23. 15. input and output voltage swing is a single ? ended measurement operating in differential mode. figure 2. output voltage amplitude (v outpp ) vs. input frequency (f in ) at ambient temperature (typical) f out , clock output frequency (ghz) output voltage amplitude (mv) figure 3. input structure 50 50 v tx v cc in x in x 400 350 300 250 200 150 100 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
NB7V586M http://onsemi.com 6 inx inx q q t plh t phl v outpp = v oh (q n ) ? v ol (q n ) v inpp = v ih (in x ) ? v il (in x ) figure 4. differential inputs driven differentially figure 5. ac reference measurement v ihd v ild v id = |v ihd(in) ? v ild(in)| inx inx figure 6. differential input driven single ? ended figure 7. differential inputs driven differentially figure 8. v th diagram figure 9. v cmr diagram in v cc gnd v ih v ihmin v ihmax v thmax v th v th v thmin v cmmin v cmmax inx v cmr v cc gnd inx inx v th v th inx inx v ilmax v il v ilmin inx v ildmax v ihdmax v id = v ihd ? v ild v ildtyp v ihdtyp v ildmin v ihdmin figure 10. typical cml output structure and termination v ccox 50 50 16 ma 50 50 v cc (receiver) gnd q q NB7V586M
NB7V586M http://onsemi.com 7 lvpecl driver v cc gnd z o = 50 v t = v cc ? 2 v z o = 50 NB7V586M in x 50 50 in x gnd figure 11. lvpecl interface lvds driver v cc gnd z o = 50 v t = open z o = 50 NB7V586M in x 50 50 in x gnd figure 12. lvds interface v cc v cc cml driver v cc gnd z o = 50 v t = v cc z o = 50 NB7V586M in x 50 50 in x gnd v cc figure 13. standard 50 load cml interface differential driver v cc gnd z o = 50 vt = v refac * z o = 50 NB7V586M in x 50 50 in x gnd v cc figure 14. capacitor ? coupled differential interface (v t connected to v refac ) *v refac bypassed to ground with a 0.01 f capacitor ordering information device package shipping ? NB7V586Mmng qfn32 (pb ? free) 74 units / rail NB7V586Mmnr4g qfn32 (pb ? free) 1000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
NB7V586M http://onsemi.com 8 package dimensions qfn32 5*5*1 0.5 p case 488am ? 01 issue o seating 32 x k 0.15 c (a3) a a1 d2 b 1 9 16 17 32 2 x 2 x e2 32 x 8 24 32 x l 32 x bottom view exposed pad top view side view d a b e 0.15 c pin one location 0.10 c 0.08 c c 25 e a 0.10 b c 0.05 c notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm terminal 4. coplanarity applies to the exposed pad as well as the terminals. plane dim min nom max millimeters a 0.800 0.900 1.000 a1 0.000 0.025 0.050 a3 0.200 ref b 0.180 0.250 0.300 d 5.00 bsc d2 2.950 3.100 3.250 e 5.00 bsc e2 e 0.500 bsc k 0.200 ??? ??? l 0.300 0.400 0.500 2.950 3.100 3.250 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.50 pitch 3.20 0.28 3.20 32 x 28 x 0.63 32 x 5.30 5.30 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 NB7V586M/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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